APPENDIX B: The On-Board Registers

The GG2 Bus+ bridgecard includes 3 software accessible registers.
Addresses are given with respect to the autoconfig base address.

REGISTER 1:	READ ONLY	Address = base + $18000,1 (16 bits wide)

bit 0: Master interrupt enable 1 = interrupts enabled, 0 = interrupts disabled

bit 1:	Wait state enable 1 = wait states enabled, 0 = wait states disabled
	
bit 2:	IRQ3 status	1 = interrupt pending,  0 = no interrupt pending
	
bit 3:	IRQ4 status	1 = interrupt pending,  0 = no interrupt pending
	
bit 4:	IRQ5 status	1 = interrupt pending,  0 = no interrupt pending
	
bit 5:	IRQ6 status	1 = interrupt pending,  0 = no interrupt pending
	
bit 6:	IRQ7 status	1 = interrupt pending,  0 = no interrupt pending
	
bit 7:	IRQ9 status	1 = interrupt pending,  0 = no interrupt pending
	
bit 8:	IRQ10 status	1 = interrupt pending,  0 = no interrupt pending
	
bit 9:	IRQ11 status	1 = interrupt pending,  0 = no interrupt pending
	
bit 10:	IRQ12 status	1 = interrupt pending,  0 = no interrupt pending
	
bit 11:	IRQ14 status	1 = interrupt pending,  0 = no interrupt pending
	
bit 12: IRQ15 status	1 = interrupt pending,  0 = no interrupt pending

	bits 13-15: not used

At power up, interrupts are disabled (so that bit 0 will have the value 0),
and wait states will be set to a default value controlled by the on-board
jumper.  If the jumper is set to "on", then bit 1 will be a 1, otherwise
bit 1 will have the value 0.  A system reset will reset wait state support
to its default value, but will not affect whether interrupts are enabled 
or disabled.


REGISTER 2:	READ/WRITE	Address = base + $18002,3  (16 bits wide)

When register 2 is read, it returns the same value as register 1.  However,
reading register 2 also has the effect of disabling the master interrupt
enable line, so that IBM devices can no longer interrupt the Amiga.

Writing any value to register 2 enables the master interrupt enable line,
allowing the Amiga to be interrupted by IBM devices.


REGISTER 3:	READ/WRITE	Address = base + $18004,5,6,7

Writing or reading register 3 toggles the wait state enable line between 
enabling wait states and disabling them.  The current state of the line is
reported as bit 1 of registers 1 or 2.  Two successive writes or reads of
register 3 leave the wait state enable line unchanged.  The value written
to register 3 is ignored.  The value returned from a read of register 3 is
to be ignored.